Field of the Invention
The invention relates to an integrated circuit having adjustable delay units for clock signals.
U.S. Pat. No. 5,684,421 describes a delay locked loop (DLL) which generates a time-delayed output clock signal from an input clock signal. The output clock signal has a specific phase relationship with respect to the input clock signal. An adjustable delay unit is disposed between the input and the output of the DLL. The input and the output are additionally connected to a phase detector which controls the delay time of the delay unit as a function of the phase difference that is ascertained. It is also mentioned that a further adjustable delay unit can be provided in each case between the output of the DLL and/or the input of the DLL and the phase detector. Those further adjustable delay units serve for setting the phase angle of the output clock signal with respect to the input clock signal. The phase detector always determines the phase difference between the clock signals that are fed directly to it.
U.S. Pat. No. 5,684,421 also discloses a DLL having an input clock signal which is a differential clock signal that is fed to the delay unit through a line pair. The signals on both lines of the line pair are delayed uniformly by the delay unit. Consequently, the signals on both lines of the data line pair are delayed by the same delay time and fed to circuit components connected downstream of the DLL.